module alu (
    input clk,
    input rst,
    input [2:0] s,
    input [7:0] x,
    input [7:0] y,
    input cin,
    output reg [7:0] res,
    output reg overflow
);

  reg [8:0] tmp;

  always @(*) begin
    case (s)
      3'b000: begin
        res = 8'd0;
        overflow = 1'b0;
      end
      3'b001: begin
        res = x & y;
        overflow = 1'b0;
      end
      3'b010: begin
        res = x | y;
        overflow = 1'b0;
      end
      3'b011: begin
        res = x ^ y;
        overflow = 1'b0;
      end
      3'b100: begin
        tmp = {x[7], x} + {y[7], y};
        overflow = tmp[8] ^ tmp[7];
        tmp = tmp + !cin;
        res = tmp[7:0];
        overflow = overflow ? 1'b1 : tmp[8] ^ tmp[7];
      end
      3'b101: begin
        res = x << 1;
        overflow = 1'b0;
      end
      3'b110: begin
        res = x >> 1;
        overflow = 1'b0;
      end
      3'b111: begin
        res = {x[7], x[7:1]};
        overflow = 1'b0;
      end
      default: begin
        res = res;
        overflow = overflow;
      end
    endcase
  end

endmodule
